As integrated circuit (IC) fabrication technology improves, the size of transistors tends to shrink. This enables more transistors and more complicated circuits to be fabricated on an IC die or, alternatively, a smaller die to be used for a given circuit. Smaller transistor size also supports faster operating speed and provides other benefits.
For CMOS technology, which is widely used for digital circuits and some analog circuits, a major issue with shrinking transistor size is sleep mode (or standby) power. Smaller transistor geometry results in higher electric fields, which stresses a transistor and causes oxide breakdown. To decrease the electric fields, a lower power supply voltage is often used for smaller geometry transistors. Unfortunately, the lower power supply voltage also increases the delay of the transistors from state to state, which is undesirable for high-speed circuits. To reduce the delay and improve operating speed, the threshold voltage (Vt) of the transistors is reduced. The threshold voltage determines the voltage at which the transistors turn on. However, the lower threshold voltage and smaller transistor geometry result in higher leakage current, which is the current passing through a transistor when it is turned off.
Leakage current becomes more problematic as CMOS technology scales smaller because leakage current increases at a higher rate with respect to the decrease in transistor size. Moreover, leakage current is a major issue for certain applications such as portable devices (e.g., cellular phone and portable computer). Leakage current consumes power and reduces standby time for portable devices that use battery power.
Reducing leakage current without significantly sacrificing performance is one of the major challenges in CMOS designs, especially as IC technology scales down to the 90 nm (nanometer) range and smaller. One common method of combating high leakage current in large CMOS circuit designs is to cut-off power to a CMOS circuit when it is turned off. Power may be cut off with a headswitch, a footswitch, or both. A headswitch is a switch placed between a power supply and the CMOS circuit. A footswitch is a switch placed between the CMOS circuit and circuit ground.
FIG. 1 illustrates an IC using a conventional power cut-off design including a headswitch and a footswitch.
As shown, the IC provides a global VDD power rail 110 and a global VSS ground rail 120. The IC further includes an IC logic portion 150 (e.g., a memory unit, a processor, etc.). IC logic 150 includes its own local VDD power rail 115 and local VSS ground rail 125, which are coupled to global VDD power rail 110 and global VSS ground rail 120, respectively. Local VDD power rail 115 is coupled to global VDD power rail 110 via a headswitch 130, and local VSS ground rail 125 is coupled to global VSS ground rail 120 via a footswitch 140. As discussed above, it may be advantageous for the IC to enter a sleep mode to conserve power, whereby the head and foot switches can be used to isolate the global and local rails, as is well known in the art. Conventionally, headswitch 130 may be a PMOS transistor or the like, and footswitch 140 may be an NMOS transistor or the like. The headswitch 130 and footswitch 140 operation is controlled by an enable en signal, which may be provided by a system controller or the like (not shown). In FIG. 1, the enable en signal is high when the IC is in an active mode (normal operation) and low when the IC is in a sleep mode (standby operation). It will be appreciated that designation of active and sleep modes based on the enable en signal is arbitrary, and the designation can be reversed with relatively minor changes to the design of FIG. 1.
A dual-Vt CMOS technology, as provided for by the IC of FIG. 1, allows for fabrication of both low threshold voltage (low-Vt) and high threshold voltage (high-Vt) field effect transistor (FET) devices on the same IC die. Since speed is not critical for head and foot switches, these switches (e.g., headswitch 130 and footswitch 140) may be implemented with high-Vt FET devices to reduce leakage current. The CMOS circuit (e.g., IC logic portion 150) is implemented with low-Vt FET devices for high-speed operation. During normal operation, the switches are turned on and the CMOS circuit operates with the speed advantage of the low-Vt FET devices. In sleep mode, the switches are turned off and the CMOS circuit is disabled. Since the leakage current of a high-Vt FET device may be as much as 10 to 100 times less than the leakage current of a low-Vt FET device, leakage current of the CMOS circuit is reduced by the use of high-Vt FET devices for the switches.
The method described above for reducing leakage current (i.e., with high-Vt FET devices for the power switches and low-Vt FET devices for the CMOS circuit) is adequate for some CMOS circuits. Nevertheless, even the reduced leakage current provided by the conventional designs described above may not be sufficient for certain applications.